The present invention relates to a termination impedance control circuit and a control method thereof, and more particularly to an on-die termination (ODT) control circuit for supporting a dynamic ODT operation used for a double data rate (DDR) 3 semiconductor memory device.
As the capacity/speed of a semiconductor memory device is gradually required to be increased, a DDR SDRAM (Synchronous Dynamic Random Access Memory) is developed and various new concepts are proposed to increase the data transmission speed of the semiconductor memory device. Among other things, termination resistance, i.e., impedance matching, is a very important factor to facilitate signal transmission between devices.
If impedance matching between the devices transmitting signals to each other is not properly achieved, a transmission signal may be reflected, thereby causing an error in signal transmission. However, when fixed resistance is applied to the termination of the devices to match the impedance, the impedance matching may not be properly achieved due to various factors, such as aging of integrated circuits, temperature variation, and manufacturing processes. To solve this problem, recently, there has been suggested a technology for controlling the termination resistance by adjusting the number of turn-on transistors, which are connected in parallel to each other, such that the resistance value can match with the external reference resistance value.
One of the apparatuses provided for this concept is an ODT control circuit. A conventional ODT control circuit is disclosed in Korean Patent Registration No. 10-0625298 in the title of “Circuit for controlling enable/disable operation of termination apparatus”.
If the semiconductor memory device has a level of the DDR3 SDRAM, the dynamic ODT operation must be supported in the semiconductor memory device in accordance with the specification established by JEDEC. The term “dynamic ODT operation” refers to the operation for controlling a termination resistor provided in a chip such that the termination resistor has a termination resistance value suitable for data input when a write command is input, without reestablishing a mode register set, etc.
The termination scheme and the resistance value of an interface of a semiconductor memory device may vary according to data input and data output. In the case of data output, pull-up or pull-down termination is performed relative to an input/output pad (DQ pad) to output “high” or “low” data. In the case of data input, the input/output pad (DQ pad) are pull-up or pull-down terminated with a predetermined resistance value (which is different from a resistance value upon data output) to receive data. In the case of the DDR3-level semiconductor memory device supported with the dynamic ODT operation, the ODT operation may be stably performed according to data input, i.e., even if only a write command is input into the semiconductor memory device.
A conventional ODT control circuit simply controls the enable or disable operation of an ODT circuit. However, since the dynamic ODT operation must be additionally supported to the DDR3-level semiconductor memory device, the ODT control circuit must control the start and end modes of the dynamic ODT operation of the ODT circuit according to data input/output.